Arithmetic Coding Hardware Acceleration in a SoPC platform for Advanced Video Compression
نویسندگان
چکیده
This paper investigates the algorithmic complexity of arithmetic coding in the new H264 video coding standard and proposes a coprocessor to reduce it by more than an order of magnitude. The coprocessor is based on an innovative algorithm known as the MZ-coder and maintains the original coding efficiency with a multiplication-free, non-stalling, fully pipelined architecture with modest hardware requirements. The coprocessor is tightly coupled to an opensource configurable RISC processor implementing the SPARC V8 ISA with the RISC CPU executing the rest of the H264 code. The video coding system has been integrated in a PCI-based SoPC platform and functionality and performance have been verified.
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